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ICS680-01
Networking Clock Synthesizer and Zero Delay Buffer
Description
The ICS680-01 generates four high-frequency clock outputs and a reference from a 25 MHz crystal or clock input. The device includes a low-skew, single input to four output zero delay clock buffer. It can replace multiple crystals and oscillators, saving board space and cost. The device has a power-down tri-state (PDTS) pin that place the clock outputs in a high-impedance state when pulled low. The PDTS pin includes an internal pull-up resistor.
Features
* * * * * * * * * *
Packaged in 24-pin TSSOP Available in Pb (lead) free package Replaces multiple crystals and oscillators Input crystal or clock frequency of 25 MHz Five output driver driven by external clock Duty cycle of 45/55 Operating voltage of 3.3 V Advanced, low-power CMOS process Fixed output frequencies of 25 MHz and 48 MHz Selectable output frequencies of 24 MHz, 48 MHz, 50 MHz and 66.6666 MHz
* Qx outputs replace costly discrete buffer * Low-skew buffer outputs (250 ps)
Block Diagram
VDD 5 S0 S1 PLLA Divide Logic and Output Enable Control CLK2 48M 25M CLK1
PLLB 25 MHz Crystal or Clock X1/ICLK Crystal Oscillator
PLLC
X2
External capacitors may be required.
QFB Q0 Q1 PLL/Buffer Q2 Q3 2 GND PDTS
ICLK
MDS 680-01 F Integrated Circuit Systems, Inc.
1
525 Race Street, San Jose, CA 95126
Revision 020305 tel (408) 297-1201
www.icst.com
ICS680-01 Networking Clock Synthesizer and Zero Delay Buffer
Pin Assignment
X1/ICLK GND S0 VDD CLK1 GND GND Q1 Q2 VDD Q3 Q4 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 X2 VDD PDTS S1 25M ICLK VDD QFB VDD 48M CLK2 GND
Output Clock Select Table S0
M 0 0 1 1
S1
M 0 1 0 1
CLK1 (MHz) CLK2 (MHz)
OFF 50 66.6666 50 66.6666 48 48 48 24 24
24-pin TSSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Pin Name
X1/ICLK GND S0 VDD CLK1 GND GND Q1 Q2 VDD Q3 Q4 GND CLK2 48M VDD QFB
Pin Type
XI Power Input Power Output Power Power Output Output Power Output Output Power Output Output Power Output Connect to ground.
Pin Description
Crystal input. Connect this pin to a crystal or external clock source. Select pin 0. See table above. Connect to voltage supply. Selectable output clock. See table above. Weak internal pull-down when tri-state. Connect to ground. Connect to ground. Clock output 1. Weak internal pull-down when tri-state. Clock output 2. Weak internal pull-down when tri-state. Connect to voltage supply. Clock output 3. Weak internal pull-down when tri-state. Clock output 4. Weak internal pull-down when tri-state. Connect to ground. Selectable output clock. See table above. Weak internal pull-down when tri-state. 48 MHz output clock. Weak internal pull-down when tri-state. Connect to voltage supply. Feedback pin. Internally connected.
MDS 680-01 F Integrated Circuit Systems, Inc.
2
525 Race Street, San Jose, CA 95126
Revision 020305 tel (408) 297-1201
www.icst.com
ICS680-01 Networking Clock Synthesizer and Zero Delay Buffer
Pin Number
18 19 20 21 22 23 24
Pin Name
VDD ICLK 25M S1 PDTS VDD X2
Pin Type
Power Input Output Input Power Power XO Connect to voltage supply.
Pin Description
Zero Delay Buffer Input. Weak Internal pull-up. 25 MHz reference output clock. Weak internal pull-down when tri-state. Select pin 1. See table above. Power-down tri-state. Powers down entire chip and tri-states outputs when low. Internal pull-up resistor. Connect to voltage supply. Crystal output. Connect this pin to a crystal. Float for clock input.
External Components
The ICS680-01 requires a minimum number of external components for proper operation.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS680-01. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected between VDD (pins 5 and 16) and GND (pins 6 and 15), as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance) place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Crystal Information
The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation crystal caps (pF) = (CL-6)x2 In the equation, CL is the crystal load capacitance. So for a crystal with a 16 pF load capacitance, two 20 pF[(16-6)x2] capacitors should be used
MDS 680-01 F Integrated Circuit Systems, Inc.
3
525 Race Street, San Jose, CA 95126
Revision 020305 tel (408) 297-1201
www.icst.com
ICS680-01 Networking Clock Synthesizer and Zero Delay Buffer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS680-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 125C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3.13
Typ.
+3.3
Max.
+70 +3.46
Units
C V
MDS 680-01 F Integrated Circuit Systems, Inc.
4
525 Race Street, San Jose, CA 95126
Revision 020305 tel (408) 297-1201
www.icst.com
ICS680-01 Networking Clock Synthesizer and Zero Delay Buffer
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70C
Parameter
Operating Voltage Supply Current Input High Voltage, binary inputs Input High Voltage, trinary inputs Input Low Voltage, binary inputs Input Low Voltage, trinary inputs Output High Voltage Output High Voltage Output Low Voltage Short Circuit Current Input Capacitance, Inputs Nominal Output Impedance On-Chip Pull-up Resistor, Inputs On-Chip Pull-down Resistor, Outputs
Symbol
VDD IDD VIH VIH VIL VIL VOH VOH VOL IOS CIN ZOUT RPU RPD
Conditions
No load,PDTS=1 No load,PDTS=0 PDTS, ICLK S0, S1 PDTS, ICLK S0, S1 IOH = -4 mA IOH = -12 mA IOL = 12 mA IOL = 4 mA CLK output
Min.
3.13
Typ.
3.3 32 300
Max.
3.46
Units
V mA A V V
2 VDD-0.5 0.8 0.5 VDD-0.4 2.4 0.8 0.4 50 5 20
V V V V V V mA pF k k
PDTS, SEL CLK outputs
250 250
MDS 680-01 F Integrated Circuit Systems, Inc.
5
525 Race Street, San Jose, CA 95126
Revision 020305 tel (408) 297-1201
www.icst.com
ICS680-01 Networking Clock Synthesizer and Zero Delay Buffer
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70 C
Parameter
Input Frequency Output Frequency Output Rise Time Output Fall Time Output Clock Duty Cycle Power-up Time
Symbol
fIN fOUT tOR tOF tD X1 ICLK
Conditions
Min.
Typ.
25 33 33 1.5 1.5
Max. Units
MHz MHz MHz ns ns 60 10 % ms
Q0 to Q3, QFB, Note 1 20% to 80%, Note 1 80% to 20%, Note 1 at VDD/2, Note 2 PLL lock-time from power-up to 1% of final frequency PDTS goes high until stable CLK outputs at 1% of final frequency 40
2
ms
One Sigma Clock Period Jitter Maximum Absolute Jitter tja
Configuration dependent Deviation from mean. Configuration dependent. Measured at VDD/2, Note 3 QFB, Q0 to Q3, Note 3 -350 -250
50 200
ps ps
QFB to ICLK Skew Pin-to-pin Skew Note 1: Measured with a 15 pF load.
tPD
350 250 ps
Note 2: Duty cycle is configuration dependent. Most configurations are min 45% / max 55%. Note 3: Skew is measured at 1.4 V on rising edges with a 33 MHz ICLK.
MDS 680-01 F Integrated Circuit Systems, Inc.
6
525 Race Street, San Jose, CA 95126
Revision 020305 tel (408) 297-1201
www.icst.com
ICS680-01 Networking Clock Synthesizer and Zero Delay Buffer
Package Outline and Package Dimensions (24-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
24
Millimeters Symbol Min Max
Inches Min Max
INDEX AREA
E1
E
12 D
A A1 A2 b C D E E1 e L
-- 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 7.70 7.90 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8
-- .047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.303 0.311 0.252 BASIC 0.169 0.177 0.0256 Basic .018 .030 0 8
A2 A1
A c
- Ce
b SEATING PLANE
.10 (.004)
C
L
Ordering Information
Part / Order Number
ICS680G-01 ICS680G-01T ICS680G-01LF ICS680G-01LFT
Marking
680G-01 680G-01 680G-01LF 680G-01LF
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
24-pin TSSOP 24-pin TSSOP 24-pin TSSOP 24-pin TSSOP
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C
"LF" denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 680-01 F Integrated Circuit Systems, Inc.
7
525 Race Street, San Jose, CA 95126
Revision 020305 tel (408) 297-1201
www.icst.com
ICS680-01 Networking Clock Synthesizer and Zero Delay Buffer
Revision History
Rev.
D
Originator
P.Griffith
Date
10/01/04
Description of Change
Removed power supply ramp-up time spec; added trinary input specs to DC chars; added a second Output Low Voltage spec; updated Supply Current specs from 50 to 32 mA, and 50 to 300 uA; changed pull-down resistor value from 525 to 250 kohms; changed Output Rise/Fall times from 1 to 1.5 ns Released as standard product from custom device. Add LF ordering info.
E F
P.Griffith J. Sarma
12/21/04 02/03/05
MDS 680-01 F Integrated Circuit Systems, Inc.
8
525 Race Street, San Jose, CA 95126
Revision 020305 tel (408) 297-1201
www.icst.com

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